1. Field of the Invention
This invention relates generally to network switching devices and more particularly to Fibre Channel switching devices.
2. Description of the Related Art
The Fibre Channel family of standards (developed by the American National Standards Institute (ANSI)) defines a high speed communications interface for the transfer of large amounts of data between a variety of hardware systems such as personal computers, workstations, mainframes, supercomputers, storage devices and servers that have Fibre Channel interfaces. Use of Fibre Channel is proliferating in client/server applications which demand high bandwidth and low latency I/O such as mass storage, medical and scientific imaging, multimedia communication, transaction processing, distributed computing and distributed database processing applications.
Fibre Channel offers advantages over traditional channel and network technology. Conventional channel technology (e.g., telephony) provides a point-to-point connection (or service) form one device to another. Conventional channels deliver data with high speed and low latency. Channels, however, are not suited for providing connectivity among many clients and are not suited for small-packet bursty traffic. Conventional networks provide shared access to bandwidth and are designed to handle unpredictable and bursty traffic. Networks, however, are software intensive and are not able to meet the growing bandwidth requirements of many client/server applications.
Fibre Channel is an alternative to conventional channel and network connectivity technologies and is used to deliver high speed and low latency connectivity among many clients. Fibre channel establishes logical point-to-point connectivity from a source device node (port) to a destination device node (port) (a logical port-to-port serial channel). The logical port-to-port serial channel is used to transfer data from a source device (node) to a destination device node. Each node (source and destination) has a buffer (either a send buffer or a receive buffer) and data transfer is effected by moving data from the send buffer at the source node to a receive buffer at the destination node. Because the transfer scheme is logically point-to-point (node-to-node) there is no need for Fibre Channel to handle various network protocols. With Fibre Channel, data is moved from one node to another without regard to data format or meaning.
Fibre Channel uses one of several topologies (e.g., a point to point topology, a fabric topology, or a loop topology) to establish a logical point-to-point serial channel. The Fibre Channel point to point topology connects two Fibre Channel systems directly. The Fibre Channel loop topology is an arbitrated loop with ring connections that provide arbitrated access to shared bandwidth. The Fibre Channel fabric topology uses a switching fabric built from one or more Fibre Channel switches to provide a bi-directional connection from one node to another. With the fabric topology, each Fibre Channel node (device) manages only a simple point-to-point connection between itself and the fabric and the fabric manages and effects the connection between the nodes. Each transmitting node (port) enters the address of a destination node (port) in a frame header and the fabric establishes the connection.
Conventional switching systems and methods are not suited for the high bandwidth and low latency requirements of Fibre Channel. Thus, there is a need for an improved switching system and method.
In accordance with the present invention, a switching system has a data switching path and a message switching path. The data switching path includes a shared memory and memory control circuitry to transfer data frames from a receiving port to a transmitting port with high bandwidth and low latency. The shared memory includes a plurality of memory modules configured for time sliced access (time slicing) by each port. The receiving port writes a data frame to central memory in accordance with a striping method and the transmitting port reads the data frame from central memory to effect the switching of the data frame.
In accordance with the invention, each port is assigned its own time slot for access of each memory module located in central memory. This time slot protocol (time slicing) advantageously permits simultaneous access of the central memory by a plurality of ports. Simultaneous access of central memory is possible because each accessing port is accessing a different memory module in central memory during each time slot. In accordance with the invention, data frames are striped across a plurality of memory modules in central memory. Striping is performed by dividing the data frame into sub-portions and storing each sub-portion in a portion of a memory module. Preferably, the start of the frame is stored in a first memory module and the remaining frame portions are stored in memory modules that are accessed sequentially in accordance with the time slot (time-sliced) protocol (e.g. modules corresponding to sequential time slots).
In accordance with the invention, the memory modules are configured to store each frame in a plurality of contiguous buffer lines. A buffer line is a single memory location across all memory modules. Preferably, a frame buffer comprises 32 buffer lines. Faster switching is obtained by initiating the write of a received data frame in the next available time slot rather than waiting for a time slot corresponding to the physically first memory module (e.g. at the lowest address). This means that the beginning of a frame may start be written to any memory module and not necessarily the physically first memory module. The memory module storing the beginning of the frame (e.g. the start of the frame) is identified to the transmitting port so that the transmitting port initiates reading the frame beginning at the specified memory module. The memory module corresponding to the start of the frame is determined using a counter circuit that is included in the memory control circuitry in the receiving port. The counter circuit determines the buffer line offset associated with a frame written to shared memory. The buffer line offset indicates the memory module offset within the buffer line (e.g., the buffer line offset indicates the memory module that contains the beginning of the data frame). Advantageously, the switching is initiated during the next available time slot and thus decreases switch latency and reduces circuit complexity. The memory control circuitry generates a message indicating which memory module contains the beginning of the frame and then sends the message to a transmitting port. The transmitting port reads the data frame from the central memory, also in accordance with the time sliced protocol, during the time slots it is assigned for access of the various memory modules storing the data frame.
Further in accordance with the invention, messages are passed from a first port to a second port in accordance with a barrel shift protocol. With the barrel shift protocol, a crossbar switch is configured for time-slotted switch reconfiguration in accordance with a predetermined connectivity pattern. Thus, each port has time sliced access to each other port and messages are sent from one port to another by sending the message during the time slot assigned for connection to the destination port.
In accordance with another aspect of the invention, the switch includes a plurality of input/output (I/O) ports, a central (shared) memory coupled to each of the ports, a shared memory access control circuit associated with each port and coupled to each port. The shared memory access control circuit includes receive and transmit control circuits and a counter circuit that determines the buffer line offset that corresponds to the location of the start of the data frame. The switch also includes a message crossbar circuit coupled to each port and an embedded port also coupled to the crossbar switch. The message crossbar circuit is configured to relay messages from a transmitting port to a receiving port through the crossbar switch. The switch also includes central processing circuitry including a central processing unit, bus interface circuitry, memory module, a front panel interface and external network interfaces.